1V8 (VCCAUX and VCCO_0 among other things) came up OK.
FPGA responds over JTAG! It's not a brick and it survived reflow.
Now to try bringing up the remaining rails so we can test it more thoroughly.
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1V8 (VCCAUX and VCCO_0 among other things) came up OK.
FPGA responds over JTAG! It's not a brick and it survived reflow.
Now to try bringing up the remaining rails so we can test it more thoroughly.
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Andrew Zonenberg
In response to this postGTY_VCC came up fine. GTY_VCCAUX not so, it's floating to a leakage voltage but the regulator isn't coming up.
This is a little LDO with an N-channel MOSFET as an inverting level shifter driving the enable. Solder paste print on the FET wasn't great, so reworking that will be the first step in troubleshooting.
Or wait. No, it's fed from the 3V3 rail.
So I need to bring that up first. Derp.
by Andrew Zonenberg ;
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