Breaking thread since it was getting long. Here's some beauty shots of the board.
To recap, this is the culmination of a series of crimes against PCB humanity that began back in May when I scored some $3500-list-price Kintex UltraScale+ FPGAs for $55 each on AliExpress.
I decided silicon this sketchy needed to go on an equally sketchy PCB. So I designed (and back burnered for a bit due to life happenings) a 4-layer PCB, 2S2P stackup, on OSHPark. For the lulz.
Because come on, who doesn't want to put two lanes of 100GbE and four of 25GbE on a cheap batch-fab PCB?
There were a few bugs in the design that I successfully worked around with various levels of sketchiness, including DIY via-in-pad filling for some vias that I accidentally put in BGA pads (forgetting for a second that I wasn't doing this board at a "real" fab with plated and filled vias) and didn't catch during design review.
Power rails - all OK although the on/off and PGOOD signals on VCCINT don't work due to what I suspect is a bad rework job
Supervisor MCU - performing nominally
Main MCU - responds over JTAG but not further tested to date
FPGA - appears fine, successfully ran a trivial test bitstream that echoes an input clock out an LVDS HPIO pair.
Tonight's goal is to try and bring up some of the GTYs and at least get a PRBS out.
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Andrew Zonenberg
In response to this postI think that'll do nicely.
Not bad for a 4-layer board.
@azonenberg Do you have scope enough to measure when you crank it to 25Gbps?
by AMS ;
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